The next state is dependent on present stateĬ. The next state is dependent on previous stateī. The characteristic equation of D-flip-flop implies that _Ī. D-flip-flops stores the value on the data line.ġ5. Due to erasing the data from the flip-flopĬlarification: Due to its capability to transfer the data into flip-flop. Due to its capability to transfer the data into flip-flopĭ. Due to its capability to store data in flip-flopĬ. Due to its capability to receive data from flip-flopī. Why do the D flip-flops receive its designation or nomenclature as ‘Data Flip-flops’?Ī. While a negative edge-triggered D flip-flop will store a 0 when the D input is HIGH and the clock transitions from HIGH to LOW.ġ4. The D input is HIGH and the clock is HIGHĬlarification: A positive edge-triggered D flip-flop will store a 1 when the D input is HIGH and the clock transitions from LOW to HIGH.
The D input is HIGH and the clock is LOWĭ. The D input is HIGH and the clock transitions from LOW to HIGHĬ. The D input is HIGH and the clock transitions from HIGH to LOWī. A positive edge-triggered D flip-flop will store a 1 when _Ī. So, if D = 1 then in the next stage output will be 1 and hence the stage will be changed.ġ3. Earlier, the DFF is in a clear state (output is 0). Which of the following input actions will cause it to change states?Ĭlarification: PGT refers to Positive Going Transition and NGT refers to negative Going Transition. A D flip-flop utilizing a PGT clock is in the CLEAR state. The main phenomenon of the D flip-flop is that the o/p will follow the i/p when the enable pin is HIGH.ġ2. The input is toggled into the flip-flop on the leading edge of the clock and is passed to the output on the trailing edge of the clockĬlarification: Edge-triggered flip-flop means the device will change state during the rising or falling edge of the clock pulse. When both inputs are LOW, an invalid state existsĭ. The output will follow the input on the leading edge of the clockĬ. If both inputs are HIGH, the output will toggleī. Which of the following describes the operation of a positive edge-triggered D flip-flop?Ī. The output complement follows the input when enabledĬlarification: If the clock is HIGH then the D flip-flop operates and we know that input equals to output in case of D flip flop. Only one of the inputs can be HIGH at a timeĭ. Q output follows the input D when the enable is HIGHĬ. Which of the following is correct for a D latch?ī. And in D flip-flop output follows the input. The Q output is HIGH regardless of EN’s input stateĬlarification: Latch is nothing but flip flop which holds the o/p or i/p state. The Q output follows the D input when EN is HIGHĭ. The Q output is opposite the D input when EN is LOWĬ. The Q output follows the D input when EN is LOWī. Q output follows the input D when the enable is HIGHĬlarification: If clock is high then the D flip-flop operate and we know that input is equals to output in case of D flip-flop. The output complement follows the input when enabledĭ. Only one of the inputs can be HIGH at a timeĬ. The output toggles if one of the inputs is held HIGHī. Which of the following is correct for a gated D flip-flop?Ī. Hence, for every negative trigger pulse, the logic at input D is shifted to Output Q.Ĩ. The Q output is ALWAYS identical to the D inputĬlarification: By the truth table of D flip flop, we can observe that Q always depends on D. The Q output is ALWAYS identical to the D input when CLK = PGTĭ. The Q output is ALWAYS identical to the CLK input if the D input is HIGHĬ. The logic level at the D input is transferred to Q on NGT of CLKī. Which statement describes the BEST operation of a negative-edge-triggered D flip-flop?Ī. In D flip-flop, if clock input is HIGH & D=1, then output is _Ĭlarification: If clock input is HIGH & D=1, then output is 0. In D flip-flop, if clock input is LOW, the D input _Ĭlarification: In D flip-flop, if clock input is LOW, the D input has no effect, since the set and reset inputs of the NAND flip-flop are kept HIGH.Ħ. A D flip-flop can be constructed from an _ flip-flop.Ĭlarification: A D flip-flop can be constructed from an S-R flip-flop by inserting an inverter between S and R and assigning the symbol D to the S input.ĥ. The D flip-flop has _ output/outputs.Ĭlarification: The D flip-flop has two outputs: Q and Q complement. It stores the value on the data line.Ĭlarification: The D flip-flop has one input. In D flip-flop, D stands for _Ĭlarification: The D of D-flip-flop stands for “data”. Digital Electronics/Circuits Multiple Choice Questions on “D Flip Flop”.ġ.